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Microcomputer Components
8-Bit CMOS Microcontroller
C517A
Data Sheet 10.97
C517A Data Sheet Revision History: Previous Version: Page Page (in previous (in current Version) Version) Current Version: 10.97 none Subjects (major changes since last revision)
Edition 10.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
8-Bit CMOS Microcontroller
C517A
Advance Information
* * * * * * * * * *
Full upward compatibility with SAB 80C517A/83C517A-5 Up to 24 MHz external operating frequency - 500 ns instruction cycle at 24 MHz operation Superset of the 8051 architecture with 8 datapointers On-chip emulation support logic (Enhanced Hooks Technology TM) 32K byte on-chip ROM (with optional ROM protection) - alternatively up to 64K byte external program memory Up to 64K byte external data memory 256 byte on-chip RAM Additional 2K byte on-chip RAM (XRAM) Seven 8-bit parallel I/O ports Two input ports for analog/digital input (further features are on next page)
On-Chip Emulation Support Module
Oscillator Watchdog
Watchdog Timer T0 T2 T1 10-Bit A/D Converter
XRAM 2K x 8
RAM 256 x 8
Port 0 Port 1
I/O I/O I/O I/O I/O
Power Saving Modes
CCU
Compare Timer
CPU (8 Datapointer)
MDU Port 2
ROM 32k x 8 Port 8 Port 7 Port 6 Port 5
Port 3 Port 4
8 Bit USART
8 Bit UART
Analog/ Analog/ Digital Digital Input Input
I/O
I/O
MCA03317
Figure 1 C517A Functional Units Semiconductor Group 3 1997-10-01
C517A
Features (cont'd):
* *
* * * *
* * *
Two full duplex serial interfaces (USART) - 4 operating modes, fixed or variable baud rates - programmable baud rate generators Four 16-bit timer/counters - Timer 0 / 1 (C501 compatible) - Timer 2 for 16-bit reload, compare, or capture functions - Compare timer for compare/capture functions Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs 10-bit A/D converter - 12 multiplexed analog inputs - Built-in self calibration Extended watchdog facilities - 15-bit programmable watchdog timer - Oscillator watchdog Power saving modes - Slow down mode - Idle mode (can be combined with slow down mode) - Software power-down mode - Hardware power-down mode 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels P-MQFP-100 packages Temperature Ranges: SAB-C517A TA = 0 to 70 C SAF-C517A TA = -40 to 85 C SAH-C517A TA = -40 to 110 C
Table 1 Ordering Information Type SAB-C517A-4RM SAF-C517A-4RM Ordering Code Q67120-DXXXX Q67120-DXXXX Package Description (8-Bit CMOS microcontroller)
P-MQFP-100-2 with mask programmable ROM (18 MHz) P-MQFP-100-2 with mask programmable ROM (18 MHz) ext. temp. - 40 C to 85 C P-MQFP-100-2 with mask programmable ROM (24 MHz) P-MQFP-100-2 with mask programmable ROM (24 MHz) ext. temp. - 40 C to 85 C P-MQFP-100-2 for external memory (18 MHz) P-MQFP-100-2 for external memory (18 MHz) ext. temp. - 40 C to 85 C P-MQFP-100-2 for external memory (24 MHz)
SAB-C517A-4R24M Q67120-DXXXX SAF-C517A-4R24M Q67120-DXXXX SAB-C517A-LM SAF-C517A-LM SAB-C517A-L24M Q67127-C1071 Q67127-C1063 Q67127-C1072
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C517A
Note: Versions for extended temperature ranges - 40 C to 110 C (SAH-C517A) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.
VCC
VSS
Port 7 8-bit Analog/ Digital Input Port 8 4-bit Analog/ Digital Input XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD OWE RO HWPD
Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O
C517A
Port 3 8-Bit Digital I/O Port 4 8-Bit Digital I/O Port 5 8-Bit Digital I/O Port 6 8-Bit Digital I/O
VAREF VAGND
MCL03318
Figure 2 Logic Symbol Additional Literature For further information about the C517A the following literature is available: Title C517A 8-Bit CMOS Microcontroller User's Manual C500 Microcontroller Family Architecture and Instruction Set User's Manual C500 Microcontroller Family - Pocket Guide Ordering Number B158-H7053-X-X-7600 B158-H6987-X-X-7600 B158-H6986-X-X-7600
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CC4/INT2/P1.4 N.C. N.C. N.C. N.C. CC3/INT6/P1.3 CC2/INT5/P1.2 CC1/INT4/P1.1 CC0/INT3/P1.0 V SS VCC XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA N.C. P0.0/AD0 P0.1/AD1 N.C. N.C. P0.2/AD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P1.5/T2EX P1.6/CLKOUT P1.7/T2 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 N.C. N.C. P7.0/AIN0 P7.1/AIN1 P7.2/AIN2 P7.3/AIN3 P7.4/AIN4 P7.5/AIN5 P7.6/AIN6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C517A
P7.7/AIN7 VAGND VAREF N.C. N.C. N.C. N.C. RESET P4.7/CM7 P4.6/CM6 P4.5/CM5 P4.4/CM4 P4.3/CM3 PE/SWD P4.2/CM2 P4.1/CM1 P4.0/CM0 VCC VSS RO P8.3/AIN11 P8.2/AIN10 P8.1/AIN9 P8.0/AIN8 P6.7 P6.6 P6.5 N.C. N.C. N.C.
P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 HWPD CCM7/P5.7 CCM6/P5.6 CCM5/P5.5 CCM4/P5.4 CCM3/P5.3 CCM2/P5.2 CCM1/P5.1 CCM0/P5.0 OWE ADST/P6.0 RxD1/P6.1 TxD1/P6.2 P6.3 P6.4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCP03319
Figure 3 Pin Configuration P-MQFP-100 Package (Top View)
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Table 2 Pin Definitions and Functions Symbol P1.0 - P1.7 Pin Number P-MQFP-100 9 - 6, 1, 100 - 98 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3 CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 INT4 CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 INT5 CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 INT6 CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger input P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input Ground (0V) during normal, idle, and power down operation. Supply voltage during normal, idle, and power down mode. I/O*) Function
9 8 7 6 1 100 99 98 VSS VCC
*) I = Input O = Output
10, 62 11, 63
- -
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Table 2 Pin Definitions and Functions (cont'd) Symbol XTAL2 Pin Number P-MQFP-100 12 - XTAL2 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. XTAL1 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. I/O*) Function
XTAL1
13
-
P2.0 - P2.7
14 - 21
I/O
PSEN
22
O
ALE
23
O
*) I = Input O = Output
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Table 2 Pin Definitions and Functions (cont'd) Symbol EA Pin Number P-MQFP-100 24 I External Access Enable When held high, the C517A executes instructions from the internal ROM as long as the PC is less than 8000H. When held low, the C517A fetches all instructions from external program memory. For the C517A-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C517A. External pullup resistors are required during program verification. Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C517A. A low level for a longer period will force the part into hardware power down mode with the pins floating. There is no internal pullup resistor connected to this pin. Port 5 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 5 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. This port also serves the alternate function "Concurrent Compare" and "Set/Reset Compare". The secondary functions are assigned to the port 5 pins as follows: CCM0 to CCM7 P5.0 to P5.7: concurrent compare or Set/Reset lines I/O*) Function
P0.0 - P0.7
26, 27, 30 - 35
I/O
HWPD
36
I
P5.0 - P5.7
44 - 37
I/O
*) I = Input O = Output
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Table 2 Pin Definitions and Functions (cont'd) Symbol OWE Pin Number P-MQFP-100 45 I Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog. When left unconnected this pin is pulled high by a weak internal pull-up resistor. The logic level at OWE should not be changed during normal operation. When held at low level the oscillator watchdog function is turned off. During hardware power down the pullup resistor is switched off. Port 6 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 6 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 6 also contains the external A/D converter control pin and the transmit and receive pins for the serial interface 1. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 6, as follows: P6.0 ADST external A/D converter start pin P6.1 RxD1 receiver data input of serial interface 1 P6.2 TxD1 transmitter data input of serial interface 1 Port 8 is a 4-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/ low voltages, and for the higher 4-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P8.0 - P8.3 AIN8 - AIN11 analog input 8 - 14 Reset Output This pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watchdog reset. The RO is active low. I/O*) Function
P6.0 - P6.7
46 - 50, 54 - 56
I/O
46 47 48 P8.0 - P8.3 57 - 60 I
RO
61
O
*) I = Input O = Output
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Table 2 Pin Definitions and Functions (cont'd) Symbol P4.0 - P4.7 Pin Number P-MQFP-100 64 - 66, 68 - 72 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1's written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Power saving mode enable / Start watchdog timer A low level at this pin allows the software to enter the power saving modes (idle mode, slow down mode, and power down mode). In case the low level is also seen during reset, the watchdog timer function is off on default. Usage of the software controlled power saving modes is blocked, when this pin is held at high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. During hardware power down the pullup resistor is switched off. RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C517A. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . Reference voltage for the A/D converter Reference ground for the A/D converter Port 7 is an 8-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the lower 8-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P7.0 - P7.7 AIN0 - AIN7 analog input 8 - 14 I/O*) Function
PE/SWD
67
I
RESET
73
I
VAREF VAGND P7.0 - P7.7
78 79 87 - 80
- -
*) I = Input O = Output
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Table 2 Pin Definitions and Functions (cont'd) Symbol P3.0 - P3.7 Pin Number P-MQFP-100 90 - 97 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RxD0 Receiver data input (asynch.) or data input/output (synch.)of serial interface 0 P3.1 TxD0 Transmitter data output (asynch.) or clock output (synch.) of serial interface 0 P3.2 INT0 External interrupt 0 input / timer 0 gate control input P3.3 INT1 External interrupt 1 input / timer 1 gate control input P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR WR control output; latches the data byte from port 0 into the external data memory P3.7 RD RD control output; enables the external data memory Not connected These pins of the P-MQFP-100 package need not be connected. I/O*) Function
90 91 92 93 94 95 96
97 N.C. 2 - 5, 25, 28, 29, 32, 43, 44, 51 - 53, 74 - 77 88, 89 -
*) I = Input O = Output
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C517A
Oscillator Watchdog XTAL1 XTAL2 ALE PSEN EA PE/SWD RESET HWPD RO OWE Timer 1 Timer 2 Capture Compare Unit Compare Timer Port 3 Serial Channel 0 Programmable Baud Rate Generator Serial Channel 1 Programmable Baud Rate Generator Interrupt Unit Port 5 Port 4 Port 4 8-Bit Digital I/O Port 5 8-Bit Digital I/O Port 6 8-Bit Digital I/O Port 7 8-Bit Analog/ Digital Input Port 8 4-Bit Analog/ Digital Input Port 2 Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O Port 1 Port 1 8-Bit Digital I/O Programmable Watchdog Timer Timer 0 CPU 8 Datapointer Emulation Support Logic Port 0 Port 0 8-Bit Digital I/O OSC & Timing RAM 256 x 8 XRAM 2k x 8 ROM 32k x 8
Port 6
VAREF VAGND
S&H
A/D Converter 10 Bit Analog MUX
Port 7
Port 8
C517A
MCB03320
Figure 4 Block Diagram of the C517A
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CPU The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1s (24 MHz: 500 ns). Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
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Memory Organization The C517A CPU manipulates operands in the following five address spaces: - - - - - up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R) up to 64 Kbyte of external data memory 256 bytes of internal data memory 2K bytes of internal XRAM data memory a 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C517A.
FFFF H int. (XMAP0 = 0) ext. ext. (XMAP0 = 1)
FFFF H
F800 H 8000 H 7FFF H int. (EA = 1) ext. (EA = 0) 0000 H "Code Space" ext. F7FF H
Indirect Address FF H Internal RAM 80 H Internal RAM
Direct Address Special Function Regs. 7F H FF H
80 H
0000 H "Data Space"
00 H "Internal Data Space"
MCB03321
Figure 5 C517A Memory Map
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.
a)
b)
& + RESET RESET
C517A
c)
C517A
+
RESET
C517A
MCS03323
Figure 6 Reset Circuitries
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Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.
Crystal Oscillator Mode C XTAL1 3.5 - 24 MHz XTAL2 C Crystal Mode: C = 20 pF 10 pF (Incl. Stray Capacitance)
Driving from External Source N.C. XTAL1
External Oscillator Signal
XTAL2
MCS03245
Figure 7 Recommended Oscillator Circuitries
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C517A
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System interface to emulation hardware
SYSCON PCON TCON C500 MCU opt. I/O Ports
RESET EA ALE PSEN Port 0 Port 2 Port 3 Port 1
RSYSCON RPCON RTCON Enhanced Hooks Interface Circuit RPORT RPORT 2 0 TEA TALE TPSEN EH-IC
Target System Interface
MCS03254
Figure 8 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.
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Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C517A are listed in table 3 and table 4. In table 3 they are organized in groups which refer to the functional blocks of the C517A. Table 4 illustrates the contents of the SFRs in numeric order of their addresses.
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Table 3 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register, High Byte A/D Converter Data Register, Low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register 0 Interrupt Request Control Register 1 Timer 0/1 Control Register Timer 2 Control Register Serial Channel 0 Control Register Compare Timer Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Address Contents after Reset E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H D8H 1) DCH D9H DAH A8H 1) B8H 1) 9AH A9H B9H C0H 1) D1H 88H 1) C8H 1) 98H 1) E1H EFH E9H EAH EBH ECH EDH EEH 88H 1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H XXXX X000B 3) 00H 07H 00H 0XXX 0000B 3) 00H 00XX XXXXB 3 00H 00H XX00 00X0B 3) 00H XX00 0000B 3) 00H 00H 00H 00H 00H 0X00 0000B 3) 0XXXXXXXB 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) 00H 00H 00H 00H 00H 00H
ADCON0 2) A/DConverter ADCON1 ADDATH ADDATL
Interrupt System
IEN0 2) IEN1 2) IEN2 IP0 2) IP1 IRCON0 2) IRCON1 TCON 2) T2CON 2) S0CON 2) CTCON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 TCON TH0 TH1 TL0 TL1 TMOD
2)
MUL/DIV Unit
Timer 0 / Timer 1
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) `X' means that the value is undefined and the location is reserved
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Table 3 Special Function Registers - Functional Blocks (cont'd) Block Compare/ Capture Unit (CCU) Timer 2 Symbol CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL Name Address Contents after Reset C1H C9H C3H C5H C7H CFH C2H C4H C6H CEH F6H D3H D5H D7H E3H E5H E7H F3H F5H D2H D4H D6H E2H E4H E6H F2H F4H F7H CBH CAH A1H A2H A3H A4H A5H A6H E1H DFH DEH CDH CCH C8H 1) C0H 1) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0X00 0000B 3) 00H 00H 00H 00H 00H 00H
Compare/Capture Enable Register Compare/Capture 4 Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 4, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Comp./Rel./Capt. Register High Byte Comp./Rel./Capt. Register Low Byte COMSETL Compare Set Register Low Byte COMSETH Compare Set Register, High Byte COMCLRL Compare Clear Register, Low Byte COMCLRH Compare Clear Register, High Byte SETMSK Compare Set Mask Register CLRMSK Compare Clear Mask Register CTCON 2) Compare Timer Control Register Compare Timer Rel. Register, High Byte CTRELH Compare Timer Rel. Register, Low Byte CTRELL TH2 Timer 2, High Byte Timer 2, Low Byte TL2 T2CON 2) Timer 2 Control Register IRCON0 2) Interrupt Request Control Register 0
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) `X' means that the value is undefined and the location is reserved
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Table 3 Special Function Registers - Functional Blocks (cont'd) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 XPAGE
SYSCON 2)
Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit Page Address Register for Extended On-Chip RAM System/XRAM Control Register A/D Converter Control Register Power Control Register Serial Channel 0 Buffer Register Serial Channel 0 Control Register Serial Channel 0 Reload Reg., Low Byte Serial Channel 0 Reload Reg., High Byte Serial Channel 1 Buffer Register Serial Channel 1 Control Register Serial Channel 1 Reload Reg., Low Byte Serial Channel 1 Reload Reg., High Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Watchdog Timer Reload Register Power Control Register
Address Contents after Reset 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) F8H 1) FAH DBH DDH 91H B1H D8H 1) 87H 99H 98H 1) AAH BAH 9CH 9BH 9DH BBH A8H1) B8H 1) A9H 86H 87H FFH FFH FFH FFH FFH FFH FFH - - 00H XXXX XX01B 3) 00H 00H XXH 3) 00H D9H XXXX XX11B 3) XXH 3) 0X00 0000B 3) 00H XXXX XX11B 3) 00H 00H 00H 00H 00H
XRAM
Serial Channels
ADCON0 2) PCON 2) S0BUF S0CON S0RELL S0RELH S1BUF S1CON S1RELL S1RELH
Watchdog IEN0 2) IEN1 2) IP0 2) WDTREL Pow. Sav. PCON 2) Modes
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) `X' means that the value is undefined and the location is reserved.
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H SP 82H 83H 83H DPL DPH FFH 07H 00H .7 .7 .7 .7 WDTPSEL TF1 GATE .7 .7 .7 .7 T2 .7 - SM0 .7 - SM .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
.6 .6 .6 .6 .6
.5 .5 .5 .5 .5 IDLS TF0 M1 .5 .5 .5 .5 T2EX .5 - SM20 .5 ECR SM21 .5 .5 .5 .5 .5 .5
.4 .4 .4 .4 .4 SD TR0 M0 .4 .4 .4 .4 INT2 .4 - REN0 .4 ECS REN1 .4 .4 .4 .4 .4 .4
.3 .3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 INT6 .3 - TB80 .3 ECT TB81 .3 .3 .3 .3 .3 .3
.2 .2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 INT5 .2 .2 RB80 .2 ECMP RB81 .2 .2 .2 .2 .2 .2
.1 .1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 INT4 .1 .1 TI0 .1 - TI1 .1 .1 .1 .1 .1 .1
.0 .0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 INT3 .0 .0 RI0 .0 ES1 RI1 .0 .0 .0 .0 .0 .0
00H WDTREL 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H XXXXX000B 00H XXH XX0000X0B 0X000000B XXH 00H FFH
87H PCON 88H 2) TCON 89H 8AH 8BH 8CH 8DH TMOD TL0 TL1 TH0 TH1
SMOD PDS TR1 C/T .6 .6 .6 .6 CLKOUT .6 - SM1 .6 - - .6 .6 .6 .6 .6 .6
90H 2) P1 91H 92H XPAGE DPSEL
98H 2) S0CON 99H S0BUF 9AH 9BH 9CH 9DH A1H A2H A3H IEN2 S1CON S1BUF S1RELL
A0H2) P2
COMSETL 00H COMSETH 00H COMCLRL 00H
1) `X' means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) A4H A5H A6H A9H
COMCLRH 00H
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
.7 .7 .7 EAL .7 RD -
.6 .6 .6 WDT .6 WR -
.5 .5 .5 ET2 .5 T1 -
.4 .4 .4 ES0 .4 .4 T0 - EX5 .4 - - IEX5
.3 .3 .3 ET1 .3 .3 INT1 - EX4 .3 - - IEX4
.2 .2 .2 EX1 .2 .2 INT0 - EX3 .2 - - IEX3
.1 .1 .1 ET0 .1 .1 TxD0
.0 .0 .0 EX0 .0 .0 RxD0
SETMSK 00H CLRMSK 00H IP0 00H 00H D9H FFH
A8H2) IEN0 AAH S0RELL B0H2) P3 B1H
OWDS WDTS .5
SYSCON XXXXXX01B IP1 00H XX000000B XXXXXX11B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
XMAP1 XMAP0
B8H2) IEN1 B9H
EXEN2 SWDT EX6 - - - EXF2 COCA H3 .7 .7 .7 .7 .7 .7 T2PS - - - TF2 .5 - - IEX6
EX2 .1 .1 .1 IEX2
EADC .0 .0 .0 IADC COCA L0 .0 .0 .0 .0 .0 .0 T2I0
BAH S0RELH BBH S1RELH C0H2) IRCON0 C1H C2H C3H C4H C5H C6H C7H C9H CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 CC4EN
COCAL COCA 3 H2 .6 .6 .6 .6 .6 .6 I3FR .5 .5 .5 .5 .5 .5 I2FR
COCAL COCA 2 H1 .4 .4 .4 .4 .4 .4 T2R1 .3 .3 .3 .3 .3 .3 T2R0
COCAL COCA 1 H0 .2 .2 .2 .2 .2 .2 T2CM .1 .1 .1 .1 .1 .1 T2I1
C8H2) T2CON
COCO COCO COCO COCO COCO COCA EN1 N2 N1 N0 EN0 H4
COCA COMO L4
1) `X' means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) CAH CRCL CBH CRCH CCH TL2 CDH TH2 CEH CCL4 CFH CCH4 D0H2) PSW D1H D2H D3H D4H D5H D6H D7H IRCON1 CML0 CMH0 CML1 CMH1 CML2 CMH2 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H .7 .7 .7 .7 .7 .7 CY .7 .7 .7 .7 .7 .7 BD .9 .1 .7 ADCL - .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
.6 .6 .6 .6 .6 .6 AC .6 .6 .6 .6 .6 .6 CLK .8 .0 .6 - - .6 .6 .6
.5 .5 .5 .5 .5 .5 F0 .5 .5 .5 .5 .5 .5 ADEX .7 - .5 - - .5 .5 .5 ICR .5
.4 .4 .4 .4 .4 .4 RS1 .4 .4 .4 .4 .4 .4 BSY .6 - .4 - - .4 .4 .4 ICS .4
.3 .3 .3 .3 .3 .3 RS0 .3 .3 .3 .3 .3 .3 ADM .5 - .3 MX3 .3 .3 .3 .3 CTF .3
.2 .2 .2 .2 .2 .2 OV .2 .2 .2 .2 .2 .2 MX2 .4 - .2 MX2 .2 .2 .2 .2 CLK2 .2
.1 .1 .1 .1 .1 .1 F1 .1 .1 .1 .1 .1 .1 MX1 .3 - .1 MX1 .1 .1 .1 .1 CLK1 .1
.0 .0 .0 .0 .0 .0 P .0 .0 .0 .0 .0 .0 MX0 .2 - .0 MX0 .0 .0 .0 .0 CLK0 .0
ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0
D8H2) ADCON0 00H D9H ADDATH 00H DAH ADDATL DBH P7 00XXXXXXB -
DCH ADCON1 0XXX0000B DDH P8 DEH CTRELL DFH CTRELH E0H2) ACC E1H E2H CTCON CML3 - 00H 00H 00H 0X00. 0000B 00H
T2PS1 - .7 .6
1) `X' means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) E3H E4H E5H E6H E7H E9H CMH3 CML4 CMH4 CML5 CMH5 MD0 00H 00H 00H 00H 00H FFH XXH XXH XXH XXH XXH XXH 0XXX. XXXXB 00H 00H 00H 00H 00H 00H 00H FFH FFH .7 .7 .7 .7 .7 CM7 .7 .7 .7 .7 .7 .7 MDEF .7 .7 .7 .7 .7 .7 .7 CCM7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
.6 .6 .6 .6 .6 CM6 .6 .6 .6 .6 .6 .6
.5 .5 .5 .5 .5 CM5 .5 .5 .5 .5 .5 .5
.4 .4 .4 .4 .4 CM4 .4 .4 .4 .4 .4 .4 SC.4 .4 .4 .4 .4 .4 .4 .4 CCM4 .4
.3 .3 .3 .3 .3 CM3 .3 .3 .3 .3 .3 .3 SC.3 .3 .3 .3 .3 .3 .3 .3 CCM3 .3
.2 .2 .2 .2 .2 CM2 .2 .2 .2 .2 .2 .2 SC.2 .2 .2 .2 .2 .2 .2 .2 CCM2 TxD1
.1 .1 .1 .1 .1 CM1 .1 .1 .1 .1 .1 .1 SC.1 .1 .1 .1 .1 .1 .1 .1 CCM1 RxD1
.0 .0 .0 .0 .0 CM0 .0 .0 .0 .0 .0 .0 SC.0 .0 .0 .0 .0 .0 .0 .0 CCM0 ADST
E8H2) P4 EAH MD1 EBH MD2 ECH MD3 EDH MD4 EEH MD5 EFH ARCON
MDOV SLR .6 .6 .6 .6 .6 .6 .6 CCM6 .6 .5 .5 .5 .5 .5 .5 .5 CCM5 .5
F0H2) B F2H F3H F4H F5H F6H F7H FAH CML6 CMH6 CML7 CMH7 CMEN CMSEL P6
F8H2) P5
1) `X' means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers
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Digital I/O Ports The C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P6 are performed via their corresponding special function registers P0 to P6. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 7 (8-bit) an 8 (4-bit) are input ports only and provide two functions. When used as digital inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines. When used for analog inputs the desired analog channel is selected by a four-bit field in SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P7 or P8. This will have no effect. If a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same time by byte instructions. Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However, care must be taken that all bits of P7 and P8 that have an undetermined value caused by their analog function are masked.
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 5: Table 5 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops TMOD M1 0 1 1 1 M0 0 1 0 1 internal Input Clock external (max)
fOSC/12x32
fOSC/24x32
fOSC/12
fOSC/24
In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the input clock logic.
f OSC
/ 12 C/T TMOD 0
f OSC/12
P3.4/T0 P3.5/T1 max f OSC/24 TR 0/1 TCON Gate TMOD P3.2/INT0 P3.3/INT1 =1
_ <1
Timer 0/1 Input Clock 1 Control &
MCS01768
Figure 9 Timer/Counter 0 and 1 Input Clock Logic Semiconductor Group 28 1997-10-01
C517A
Compare / Capture Unit (CCU) The compare/capture unit is one of the C517A's most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature and an array of 13 compare or compare/capture registers. A set of six control registers is used for flexible adapting of the CCU to a wide variety of user's applications. The block diagram in figure 10 shows the general configuration of the CCU. All CC1 to CC4 registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done individually for every single register - is combined with an automatic selection of one of the two possible compare modes.
(CTREL) 16-bit Reload "Internal Bus"
(CM0)
Prescaler
Compare Timer Max.Clock = f OSC/2 8x 16-bit Compare Shadow Latch
Port Control Logik
P4I/OLatch
CC4EN
Prescaler
(CM7) Timer 2 Capt./Comp. 4 (CC4) Max.Clock = f OSC /12 Capt./Comp. 3 (CC3) Capt./Comp. 2 (CC2) Capt./Comp.1 (CC1) 16-bit Rel.Capt. (CRC) Comp.
P5I/OLatch
Port Control Logik
P1I/OLatch
MCB01577
Figure 10 Timer 2 Block Diagram
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The main functional blocks of the CCU are: - Timer 2 with fOSC/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and overflow interrupt request. - Compare timer with fOSC/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt request. - Compare/(reload/) capture register array consisting of four different kinds of registers: one 16-bit compare/reload/capture register, three 16-bit compare/capture registers, one 16-bit compare/capture register with additional "concurrent compare" feature, eight 16-bit compare registers with timer-overflow controlled loading. Table 6 shows the possible configurations of the CCU and the corresponding compare modes which can be selected. The following sections describe the function of these configurations. Table 6 CCU Configurations Assigned Timer Timer 2 Compare Register CRCH/CRCL CCH1/CCL1 CCH2/CCL2 CCH3/CCL3 CCH4/CCL4 CCH4/CCL4 Compare Output at P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2/CC4 P1.4/INT2/CC4 P5.0/CCM0 to P5.7/CCM7 P4.0/CM0 to P4.7/CM7 P5.0/CCM0 to P5.7/CCM7 P4.0/CM0 to P4.7/CM7 Possible Modes Compare mode 0, 1 + Reload Compare mode 0, 1 / capture Compare mode 0, 1 / capture Compare mode 0, 1 / capture Compare mode 0, 1 / capture Compare mode 1 "Concurrent compare"
CMH0/CML0 to CMH7/CML7 COMSET COMCLR Compare Timer CMH0/CML0 to CMH7/CML7
Compare mode 0
Compare mode 2
Compare mode 1
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Timer 2 Operation Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Gated Timer Mode: In gated timer function, the external input pin P1.7/T2 operates as a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. The external gate signal is sampled once every machine cycle. Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is sampled every machine cycle. The maximum count rate is 1/24 of the oscillator frequency. Reload of Timer 2: Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX.
OSC
Programmable Prescaler T2PS T2PS1
T2I1
T2I0
SFR T2CON
0 0 P1.7/T2 1 1
0 1 0 1
No input selected Timer stop Timer function Counter function via ext. input P1.7/T2 Gated timer function by ext. input P1.7/T2 Timer 2 Input Clock
TL2 (8 Bits)
TH2 (8 Bits)
TF2
_ <1
Interrupt
P1.5/T2EX
Sync EXEN2
EXF2
_ <1
Reload
MCB03328
Figure 11 Block Diagram of Timer 2 Semiconductor Group 31 1997-10-01
C517A
Compare Timer Operation The compare timer receives its input clock from a programmable prescaler which provides input frequencies, ranging from fOSC/2 up to fOSC/256. The compare timer is, once started, a free-running 16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register. The compare timer has - as any other timer in the C517A - their own interrupt request flags CTF. These flags are set when the timer count rolls over from all ones to the reload value. Figure 12 shows the block diagram of compare timer and compare timer 1.
f OSC /2
3-Bit Prescaler
Compare Timer
/2
/4
/8
/16
/32
/64
/128
Control (CTCON) 16
To Compare Circuitry
16-Bit Compare Timer
CTF
To Interrupt Circuitry
Overflow 16-Bit Reload (CTREL)
MCB00783
Figure 12 Compare Timer Block Diagram
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Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.
Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Timer Overflow Read Pin
MCS02661
VCC
Compare Match
Internal Bus Write to Latch
S D
Q Port Latch CLK Q R
Port Pin
Figure 13 Port Latch in Compare Mode 0
Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see figure 14) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs.
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Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Read Pin
MCS02662
VCC
Internal Bus Compare Match Write to Latch
D Shadow Latch CLK
Q
D
Q Port Latch CLK Q
Port Pin
Figure 14 Compare Function in Compare Mode 1 Compare Mode 2 In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under control of the compare registers COMSET and COMCLR. When a compare match occurs with register COMSET, a high level appears at the pins of port 5 when the corresponding bits in the mask register SETMSK are set. When a compare match occurs with register COMCLR, a low level appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set.
Port Circuit COMSET 16 Bit Comparator 16 Bit TH2 TL2 Compare Signal SETMSK Bits Internal Bus Write to Latch Read Latch
VCC
S D
Timer 2 16 Bit Comparator 16 Bit COMCLR Compare Signal CLRMSK Bits
Q Port Latch CLK Q R
Port Pin
Read Pin
MCS02663
Figure 15 Compare Function of Compare Mode 2
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Multiplication / Division Unit (MDU) This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. Table 7 describes the five general operations the MDU is able to perform. Table 7 MDU Operation Characteristics Operation 32bit/16bit 16bit/16bit 16bit x 16bit 32-bit normalize 32-bit shift L/R Result 32bit 16bit 32bit - - Remainder 16bit 16bit - - - Execution Time 6 tCY 1) 4 tCY 1) 4 tCY 1) 6 tCY 2) 6 tCY 2)
1) 1 tCY = 12 tCLCL= 1 machine cycle = 500 ns at 24 MHz oscillator frequency 2) The maximal shift speed is 6 shifts per machine cycle
The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as operand, result, and control registers. The three operation phases are shown in figure 16.
Figure 16 Operating Phases of the MDU
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For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain sequence according table 8 and 9. The order the registers are accessed determines the type of the operation. A shift operation is started by a final write operation to SFR ARCON. Table 8 Programming the MDU for Multiplication and Division Operation First Write 32Bit/16Bit MD0 MD1 MD2 MD3 MD4 MD5 MD0 MD1 MD2 MD3 MD4 MD5 D'endL D'end D'end D'endH D'orL D'orH QuoL Quo Quo QuoH RemL RemH 16Bit/16Bit MD0 MD1 MD4 MD5 MD0 MD1 MD4 MD5 D'endL D'endH D'orL D'orH QuoL QuoH RemL RemH 16Bit x 16Bit MD0 MD4 MD1 MD5 MD0 MD1 MD2 MD3 PrH M'andL M'orL M'andH M'orH PrL
Last Write First Read
Last Read
Abbreviations: D'end : Dividend, 1st operand of division D'or : Divisor, 2nd operand of division M'and : Multiplicand, 1st operand of multiplication M'or : Multiplicator, 2nd operand of multiplication Pr : Product, result of multiplication Rem : Remainder Quo : Quotient, result of division ...L : means, that this byte is the least significant of the 16-bit or 32-bit operand ...H : means, that this byte is the most significant of the 16-bit or 32-bit operand
Table 9 Programming of the MDU for a Shift or Normalize Operation Operation First write Normalize, Shift Left, Shift Right MD0 MD1 MD2 MD3 ARCON MD0 MD1 MD2 MD3 least significant byte . . most significant byte start of conversion least significant byte . . most significant byte
Last write First read
Last read
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Serial Interfaces 0 and 1 The C517A has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. The serial channel 0 is completely compatible with the serial channel of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART mode is missing. The operating modes of the serial interfaces is illustrated in table 10. The possible baudrates can be calculated using the formulas given in table 11. Table 10 Operating Modes of Serial Interface 0 and 1 Mode Serial Interface 0 0 S0CON SM0 0 SM1 0 S1CON Description SM - Shift register mode Serial data enters and exits through RxD0; TxD0 outputs the shift clock; 8-bit are transmitted/received (LSB first); fixed baud rate 8-bit UART, variable baud rate 10 bits are transmitted (through TxD0) or received (at RxD0) 9-bit UART, fixed baud rate 11 bits are transmitted (through TxD0) or received (at RxD0) 9-bit UART, variable baud rate Like mode 2 9-bit UART; variable baud rate 11 bits are transmitted (through TxD1) or received (at RxD1) 8-bit UART; variable baud rate 10 bits are transmitted (through TxD1) or received (at RxD1)
1
0
1
-
2
1
0
-
3 1 A
1 -
1 -
- 0
B
-
-
1
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C517A
For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in figure 17 and figure 18) to the serial interface which there divided by 16 - results in the actual "baud rate". Further, the abbreviation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer 1 or a dedicated baud rate generator (see figure 17). The variable baud rates for modes A and B of the serial interface 1 are derived from a dedicated baud rate generator as shown in figure 18.
Timer 1 Overflow ADCON0.7 (BD) S0CON.7 S0CON.6 (SM0/ SM1) PCON.7 (SMOD) /2 0 1 Baud Rate Clock
f OSC /2
Baud Rate Generator (S0RELH S0RELL)
0 1
Mode 1 Mode 3 Mode 2 Mode 0
/6 Note : The switch configuration shows the reset state.
Only one mode can be selected
MCS03329
Figure 17 Serial Interface 0 : Baud Rate Generation Configuration
Baud Rate Generator S1RELH .1 .0 S1RELL
f OSC /2
Input Clock
10-Bit Timer
Owerflow
Baud Rate Clock
MCS03331
Figure 18 Serial Interface 1 : Baud Rate Generator Configuration The baud rate generator block in figure 17 has the same structure (10-bit auto-reload timer) as the baud rate generator block which is shown in detail in figure 18.
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Table 11 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits BD and SMOD. Table 11 Serial Interfaces - Baud Rate Dependencies Serial Interface Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) Active Control Bits SMOD - X BD - 0 Fixed baud rate clock fosc/12 Timer 1 overflow is used for baud rate generation; SMOD controls a divide-by-2 option. Baud rate = 2SMOD x timer 1 overflow rate / 32 Baud rate generator is used for baud rate generation; SMOD controls a divide-by-2 option Baud rate = 2SMOD x oscillator frequency / 64 x (baud rate gen. overflow rate) Fixed baud rate clock fosc/32 (SMOD=1) or fosc/ 64 (SMOD=0) Baud rate generator is used for baud rate generation; SMOD controls a divide-by-2 option Baud rate = oscillator frequency / 32 x (baud rate gen. overflow rate) Baud Rates
1
Mode 2 (9-bit UART) Mode A (9-bit UART) Mode B (8-bit UART)
X -
- -
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C517A
10-Bit A/D Converter The C517A provides an A/D converter with the following features: - - - - - - - 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs 10-bit resolution Single or continuous conversion mode Internal or external start-of-conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors
The A/D converter operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The externally applied reference voltage range has to be held on a fixed value within the specifications. The main functional blocks of the A/D converter are shown in figure 19.
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IEN1 (B8 H ) EXEN2 SWDT IRCON0 (C0 H ) EXF2 P8 (DD H ) _ P7 (DB H ) P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 _ _ _ P8.3 P8.2 P8.1 P8.0 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC EX6 EX5 EX4 EX3 EX2 EADC
internal Bus
ADCON1 (DC H ) ADCL _ _ _ MX3 MX2 MX1 MX0
ADCON0 (D8 H ) BD CLK ADEX BSY ADM MX2 MX1 MX0
Port 7 Port 8 MUX S&H
Single/ Continuous Mode
ADDATH ADDATL (D9 H ) (DA H ) _ .2 .3 _ _ _ _ _ LSB .1 .4 .5 .6 .7 .8 MSB
A/D Converter
f OSC /2
Clock Prescaler /8, /4
Conversion Clock fADC Input Clock f IN Start of Conversion
VAREF VAGND
P6.0/ADST Write to ADDATL
Shaded bit locations are not used in ADC-functions
internal Bus
MCB03332
Figure 19 A/D Converter Block Diagram
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C517A
Interrupt System The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6). This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. Figure 20 to 22 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.
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P3.2/ INT0 IT0 TCON.0 RI1 UART 1 S1CON.0 TI1 S1CON.1 A/D Converter
Highest Priority Level IE0 TCON.1 EX0 IEN0.0 0003 H Lowest Priority Level
_ <1
ES1 IEN2.0
0083 H
IADC IRCON0.0 EADC IEN1.0
IP1.0
IP0.0
Timer 0 Overflow
TF0 TCON.5 ET0 IEN0.1
000B H
P1.4/ INT2/ CC4 I2FR T2CON.5 Bit addressable Request Flag is cleared by hardware
IEX2 IRCON0.1 EX2 IEN1.1
004B H EAL IEN0.7 IP1.1 IP0.1
MCS03333
Figure 20 Interrupt Structure, Overview (Part 1)
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Polling Sequence
0043 H
1997-10-01
C517A
P3.3/ INT1 IT1 TCON.2 Match in CM0-CM7
Highest Priority Level IE1 TCON.3 EX1 IEN0.2 0013 H Lowest Priority Level
ICMP0-7 IRCON1.0-7 ECMP IEN2.2
0093 H
P1.0/ INT3/ CC0
IEX3 I3FR T2CON.5 IRCON0.2 EX3 IEN1.2
0053 H IP1.2 IP0.2
Timer 1 Overflow
TF1 TCON.7 ET1 IEN0.3
001B H
Compare Timer Overflow
CTF CTCON.3 ECT IEN2.3
009B H
P1.1/ INT4/ CC1
IEX4 IRCON0.3 EX4 IEN1.3
005B H EAL IEN0.7 IP1.3 IP0.3
MCS03334
Bit addressable Request Flag is cleared by hardware
Figure 21 Interrupt Structure, Overview (Part 2)
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Polling Sequence
1997-10-01
C517A
RI0 USART 0 S0CON.0 TI0 S0CON.1 Match in COMSET ICS CTCON.4 ECS IEN2.4 00A3 H
_ <1
Highest Priority Level ES0 IEN0.4 0023 H Lowest Priority Level
P1.2/ INT5/ CC2
IEX5 IRCON0.4 EX5 IEN1.4
0063 H IP1.4 IP0.4
Timer 2 Overflow P1.5/ T2EX
TF2 IRCON0.6 EXF2 EXEN2 IRCON0.7 IEN1.7 ICR CTCON.5 ECR IEN2.5
_ <1
ET2 IEN0.5
002B H
Match in COMCLR
00AB H
P1.3/ INT6/ CC3
IEX6 IRCON0.5 EX6 IEN1.5
006B H EAL IEN0.7 IP1.5 IP0.5
MCS03335
Bit addressable Request Flag is cleared by hardware
Figure 22 Interrupt Structure, Overview (Part 3)
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Polling Sequence
1997-10-01
C517A
Table 12 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel 0 Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Serial Channel 1 Compare Match Interrupt of Compare Registers CM0-CM7 assigned to Timer 2 Compare Timer Overflow Compare Match Interrupt of Compare Register COMSET Compare Match Interrupt of Compare Register COMCLR Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 0083H 0093H Interrupt Request Flags IE0 TF0 IE1 TF1 RI0 / TI0 TF2 / EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 RI1 / TI1 ICMP0 - ICMP7
009BH 00A3H 00ABH
CTF ICS ICR
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C517A
Fail Save Mechanisms The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: - a programmable watchdog timer (WDT), with variable time-out period from 512 s up to approx. 1.1 s at 12 MHz. (256 s up to approx. 0.65 s at 24 MHz) - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of fOSC/24 up to fOSC/384. The system clock of the C517A is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.
0
7 WDTL 14 8 WDTH
f OSC /12
2
16
WDT Reset-Request IP0 (A9 H ) WDTS
-
-
-
-
-
-
WDTPSEL
External HW Reset External HW Power-Down PE/SWD 76 WDTREL (86 H ) IEN0 (A8 )H IEN1 (B8 )H
MCB03250
0
Control Logic WDT SWDT
-
-
-
Figure 23 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C517A. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor.
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C517A
Oscillator Watchdog The oscillator watchdog unit serves for four functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Restart from the hardware power down mode. If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function.
RC Oscillator
f RC 3MHz
/5
f1
Frequency Comparator
f2Delay
_ <1
Internal Reset
f2
XTAL1 On-Chip Oscillator IP0 (A9 H) OWDS
XTAL2
/2
Internal Clock
MCB03337
Figure 24 Block Diagram of the Oscillator Watchdog
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C517A
Power Saving Modes The C517A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. - Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset. - Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals, to 1/8th of their normal operating frequency and also reduces power consumption. - Software power down mode The operation of the C517A is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. This power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/ INT0. - Hardware Power down mode If pin HWPD gets active (low level) the part enters the hardware power down mode and starts a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and the port pins and several control lines enter a floating state. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level, before the power down mode is terminated. Table 13 gives a general overview of the entry and exit procedures of the power saving modes.
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Table 13 Power Saving Modes Overview Mode Entering 2-Instruction Example ORL PCON, #01H ORL PCON, #20H Leaving by Remarks
Idle mode
Occurrence of an interrupt from a peripheral unit Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Internal clock rate is reduced to 1/8 of its nominal frequency CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/8 of its nominal frequency Oscillator is stopped; contents of on-chip RAM and SFR's are maintained; Oscillator is stopped; internal reset is executed;
Slow Down Mode
In normal mode: ORL PCON,#10H With idle mode: ORL PCON,#01H ORL PCON, #30H
ANL PCON,#0EFH or Hardware Reset Occurrence of an interrupt from a peripheral unit Hardware reset
Software Power Down Mode Hardware Power Down Mode
ORL PCON, #02H ORL PCON, #40H HWPD = 0
Hardware Reset Short low pulse at pin P3.2/INT0 HWPD = 1
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Absolute Maximum Ratings Ambient temperature under bias (TA) ......................................................... Storage temperature (Tstg) .......................................................................... Voltage on VCC pins with respect to ground (VSS) ....................................... Voltage on any pin with respect to ground (VSS) ......................................... Input current on any pin during overload condition ..................................... Absolute sum of all input currents during overload condition ..................... Power dissipation........................................................................................ - 40 to 125 C - 65 C to 150 C - 0.5 V to 6.5 V - 0.5 V to VCC +0.5 V - 10 mA to 10 mA I 100 mA I TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
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DC Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V
TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C
Limit Values min. max.
for the SAB-C517A for the SAF-C517A for the SAH-C517A Unit Test Condition
Parameter Input low voltage Pins except EA,RESET,HWPD EA pin HWPD and RESET pins Input high voltage pins except RESET, XTAL2 and HWPD XTAL2 pin RESET and HWPD pin Output low voltage Ports 1, 2, 3, 4, 5, 6 Port 0, ALE, PSEN, RO Output high voltage Ports 1, 2, 3, 4, 5, 6 Port 0 in external bus mode, ALE, PSEN, RO Logic 0 input current Ports 1, 2, 3, 4, 5, 6 Logical 0-to-1 transition current, Ports 1, 2, 3, 4, 5, 6 Input leakage current Port 0, 7 and 8, EA, HWPD Input low current to RESET for reset XTAL2 PE/SWD, OWE Pin capacitance Overload current Notes see next page
Symbol
VIL VIL1 VIL2
- 0.5 - 0.5 - 0.5
0.2 VCC - 0.1 V 0.2 VCC - 0.3 V 0.2 VCC + 0.1 V
- - -
VIH VIH1 VIH2 VOL VOL1 VOH VOH1
0.2 VCC + 0.9 VCC + 0.5 0.7 VCC VCC + 0.5 0.6 VCC VCC + 0.5 - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - - 10 - - - - 0.45 0.45 - - - - - 70 - 650
V V V V V V V V V A A A A A A pF mA
- - -
I OL = 1.6 mA 1) I OL = 3.2 mA 1) I OH I OH I OH I OH
= - 80 A = - 10 A = - 800 A = - 80 A 2)
I LI I TL I LI I IL2 I IL3 I IL4 C IO IOV
V I N = 0.45 V VIN = 2 V 0.45 < V I N < VCC VI N = 0.45 V V I N = 0.45 V V I N = 0.45 V f C = 1 MHz, T A = 25 C
7) 8)
1
- 100 - 15 - 20 10
5
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C517A
Power Supply Current Parameter Active mode Idle mode Active mode with slow-down enabled Power-down mode
Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 7 = Port 8 = V CC ; XTAL1 = N.C.; XTAL2 = V SS ; PE/SWD = OWE = V SS ; HWPD = VCC for software power-down mode; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. IPD (hardware power-down mode) is independent of any particular pin connection. 4) ICC (active mode) is measured with: XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; EA = PE/SWD == VSS ; Port 0 = Port 7 = Port 8 = VCC ; HWPD = VCC ; RESET = VCC ; all other pins are disconnected. 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; RESET = VCC ; HWPD = Port 0 = Port 7 = Port 8 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected; 6) ICC (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; HWPD = VCC ; RESET = VCC ; Port 7 = Port 8 = VCC ;; EA = PE/SWD == VSS ; all other pins are disconnected. 7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 8) Not 100% tested, guaranteed by design characterization 9) The typical ICC values are periodically measured at TA = +25 C and VCC = 5 V but not 100% tested. 10)The maximum ICC values are measured under worst case conditions (TA = 0 C or -40 C and VCC = 5.5 V)
Symbol 18 MHz 24 MHz 18 MHz 24 MHz 18 MHz 24 MHz
Limit Values typ. 9) max. 10) 29.2 37.6 16.2 20.4 13.1 14.9 50 21.3 27.3 11.6 14.6 9.5 10.7 15
Unit Test Condition mA mA mA mA mA mA A
4)
ICC ICC ICC ICC ICC ICC IPD
5)
6)
VCC = 2...5.5 V 3)
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40
MCD03338
CC
mA 30
CC max CC typ
Ac
M tive
ode
e Activ
20
Idle M ode
Mod
e
10
Idle Mod
e
Active + Slow Down Mode 0
0
3.5
8
12
16
20 MHz f OSC
24
Figure 25 ICC Diagram Table 14 Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Symbol Formula 1 * fOSC + 3.3 1.4 * fOSC + 4.0 0.5 * fOSC + 2.6 0.7 * fOSC + 3.6 0.25 * fOSC + 4.95 0.3 * fOSC + 7.7
ICC typ ICC max ICC typ ICC max ICC typ ICC max
Note: fosc is the oscillator frequency in MHz. ICC values are given in mA.
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A/D Converter Characteristics
VCC = 5 V + 10%, - 15%; VSS = 0 V
TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C
for the SAB-C517A for the SAF-C517A for the SAH-C517A
4 V VAREF VCC+0.1 V; VSS-0.1 V VAGND VSS+0.2 V Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance
Notes see next page.
Symbol
Limit Values min. max.
Unit V ns ns LSB
Test Condition
1)
VAIN tS tADCC
TUE
VAGND
- - - - - -
VAREF
16 x tIN 8 x tIN 96 x tIN 48 x tIN 2 - 0.25
Prescaler / 8 Prescaler / 4 Prescaler / 8 Prescaler / 4
2)
3)
VSS+0.5V VIN VCC-0.5V 4)
RAREF RASRC CAIN
tADC / 250 k tS / 500
- 0.25 50 pF k
tADC in [ns] tS in [ns]
6)
5) 6)
2) 6)
Clock calculation table: Clock Prescaler ADCL Ratio /8 /4 1 0 tADC 8 x tIN 4 x tIN tS 16 x tIN 8 x tIN tADCC 96 x tIN 48 x tIN
Further timing conditions: tADC min = 500 ns tIN = 2 / fOSC = 2 tCLCL
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Notes: 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.
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AC Characteristics (18 MHz)
VCC = 5 V + 10%, - 15%; VSS = 0 V
TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C
for the SAB-C517A for the SAF-C517A for the SAH-C517A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 18 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN
*)
Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 18 MHz min. 2 tCLCL - 40 max. - - - 4 tCLCL - 100 - - 3 tCLCL - 75 -
Unit
max. - - - 122 - - 92 - 46 - 180 -
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
71 26 26 - 31 132 - 0 - 48 - 0
ns ns ns ns ns ns ns ns ns ns ns ns
tCLCL - 30 tCLCL - 30
-
tCLCL - 25
3 tCLCL - 35 - 0 -
tCLCL - 10
- 5 tCLCL - 98 -
tCLCL - 8
- 0
Interfacing the C517A to devices with float times up to 45 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
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AC Characteristics (18 MHz, cont'd) External Data Memory Characteristics Parameter Symbol 18 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 128 - 51 294 335 217 - 96 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 18 MHz min. 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 30 - 0 - - - 3 tCLCL - 50 4 tCLCL - 130 max. - - - 5 tCLCL - 150 - 2 tCLCL - 60 8 tCLCL - 150 9 tCLCL - 165 3 tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
233 233 81 - 0 - - - 117 92 16 11 239 16 -
tCLCL - 40 tCLCL - 45
7 tCLCL - 150
tCLCL + 40
- - - 0
tCLCL - 40
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 18 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
55.6 15 15 - -
tCLCL - tCLCX tCLCL - tCHCX
15 15
Semiconductor Group
58
1997-10-01
C517A
AC Characteristics (24 MHz)
VCC = 5 V + 10%, - 15%; VSS = 0 V
TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C
for the SAB-C517A for the SAF-C517A for the SAH-C517A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 24 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN
*)
Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 2 tCLCL - 40 max. - - - 4 tCLCL - 87 - - 3 tCLCL - 65 -
Unit
max. - - - 80 - - 60 - 32 - 148 -
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
43 17 17 - 22 95 - 0 - 37 - 0
ns ns ns ns ns ns ns ns ns ns ns ns
tCLCL - 25 tCLCL - 25
-
tCLCL - 20
3tCLCL - 30 - 0 -
tCLCL - 10
- 5 tCLCL - 60 -
tCLCL - 5
- 0
Interfacing the C517A to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Semiconductor Group
59
1997-10-01
C517A
AC Characteristics (24 MHz, cont'd) External Data Memory Characteristics Parameter Symbol 24 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 118 - 63 200 220 175 - 67 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 6 tCLCL - 70 6 tCLCL - 70 2 tCLCL - 30 - 0 - - - 3 tCLCL - 50 4 tCLCL - 97 max. - - - 5 tCLCL - 90 - 2 tCLCL - 20 8 tCLCL - 133 9 tCLCL - 155 3 tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
180 180 53 - 0 - - - 75 67 17 5 170 15 -
tCLCL - 25 tCLCL - 37
7 tCLCL - 122
tCLCL + 25
- - - 0
tCLCL - 27
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
41.7 12 12 - -
tCLCL - tCLCX tCLCL - tCHCX
12 12
Semiconductor Group
60
1997-10-01
C517A
t LHLL
ALE
t AVLL t
LLIV
t PLPH t LLPL t PLIV
PSEN
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 26 Program Memory Read Cycle
Semiconductor Group
61
1997-10-01
C517A
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 27 Data Memory Read Cycle
Semiconductor Group
62
1997-10-01
C517A
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 28 Data Memory Write Cycle
t CLCL VCC- 0.5V
0.7 VCC 0.2 VCC- 0.1
0.45V
t CHCL
t CLCX t CLCH
t CHCX
MCT00033
Figure 29 External Clock Drive on XTAL2
Semiconductor Group
63
1997-10-01
C517A
ROM Verification Characteristics for the C517A-1RM ROM Verification Mode 1 Parameter Address to valid data Symbol min. Limit Values max. 10 tCLCL ns - Unit
tAVQV
P1.0-P1.7 P2.0-P2.6
Address
New Address
t AVQV
Port 0 Data: Addresses: Data Out P0.0-P0.7 = D0-D7 P1.0-P1.7 = A0-A7 P2.0-P2.6 = A8-A14 Inputs: New Data Out PSEN = V SS ALE, EA = V IH RESET = V IL2
MCS03253
Figure 30 ROM Verification Mode 1
Semiconductor Group
64
1997-10-01
C517A
ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. - - 4 tCLCL - - 24 ns ns ns ns ns MHz - - - 8 tCLCL - 3.5 Unit
tAWD tACY tDVA tDSA tAS
1/ tCLCL
tCLCL
-
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 31 ROM Verification Mode 2
Semiconductor Group
65
1997-10-01
C517A
VCC -0.5 V
0.2 VCC+0.9 Test Points 0.2 VCC -0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 32 AC Testing: Input, Output Waveforms
VLoad +0.1 V VLoad VLoad -0.1 V
Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 33 AC Testing: Float Waveforms
Crystal Oscillator Mode
Driving from External Source N.C.
C
XTAL1 3.5-24 MHz
XTAL1
C
XTAL2 Crystal Mode : C = 20 pF 10 pF (incl. stray capacitance)
External Oscillator Signal
XTAL2
MCS03339
Figure 34 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 66 1997-10-01
C517A
Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package)
Figure 35 P-MQFP-100-2 Package Outlines
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 67
Dimensions in mm 1997-10-01
GPM05623

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